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74LVT16244 * 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
March 1999 Revised June 2005
74LVT16244 * 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
General Description
The LVT16244 and LVTH16244 contain sixteen non-inverting buffers with 3-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus oriented transmitter/receiver. The device is nibble controlled. Individual 3-STATE control inputs can be shorted together for 8-bit or 16-bit operation. The LVTH16244 data inputs include bushold, eliminating the need for external pull-up resistors to hold unused inputs. These buffers and line drivers are designed for low-voltage (3.3V) VCC applications, but with the capability to provide a TTL interface to a 5V environment. The LVT16244 and LVTH16244 are fabricated with an advanced BiCMOS technology to achieve high speed operation similar to 5V ABT while maintaining a low power dissipation
Features
s Input and output interface capability to systems at 5V VCC s Bushold data inputs eliminate the need for external pull-up resistors to hold unused inputs (74LVTH16244), also available without bushold feature (74LVT16244). s Live insertion/extraction permitted s Power Up/Down high impedance provides glitch-free bus loading s Outputs source/sink 32 mA/64 mA s Functionally compatible with the 74 series 16244 s Latch-up performance exceeds 500 mA s ESD performance:
Human-body model !2000V Machine model !200V Charged-drive model !1000V
s Also packaged in plastic Fine-Pitch Ball Grid Array (FBGA)
Ordering Code:
Order Number 74LVT16244G (Note 1)(Note 2) 74LVT16244MEA (Note 2) 74LVT16244MTD (Note 2) 74LVTH16244G (Note 1)(Note 2) 74LVTH16244MEA (Note 2) 74LVTH16244MTD (Note 2) Package Number BGA54A (Preliminary) MS48A MTD48 BGA54A MS48A MTD48 Package Description 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide 48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Note 1: Ordering code "G" indicates Trays. Note 2: Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Logic Symbol
(c) 2005 Fairchild Semiconductor Corporation
DS500151
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74LVT16244 * 74LVTH16244
Connection Diagrams
Pin Assignment for SSOP and TSSOP
Pin Descriptions
Pin Names OEn I0-I15 O0-O15 NC Description Output Enable Inputs (Active LOW) Inputs Outputs No Connect
FBGA Pin Assignments
1 A B C D E F G H J O0 O2 O4 O6 O8 O10 O12 O14 O15 2 NC O1 O3 O5 O7 O9 O11 O13 NC 3 OE1 NC VCC GND GND GND VCC NC OE4 4 OE2 NC VCC GND GND GND VCC NC OE3 5 NC I1 I3 I5 I7 I9 I11 I13 NC 6 I0 I2 I4 I6 I8 I10 I12 I14 I15
Truth Table
Inputs Pin Assignment for FBGA OE1 L L H Inputs OE2 L L H Inputs OE3 (Top Thru View) L L H Inputs OE4 L L H
H High Voltage Level L Low Voltage Level X Immaterial Z High Impedance
Outputs I0-I3 L H X O0-O3 L H Z Outputs I4-I7 L H X O4-O7 L H Z Outputs I8-I11 L H X O8-O11 L H Z Outputs I12-I15 L H X O12-O15 L H Z
Logic Diagram
Functional Description
The LVT16244 and LVTH16244 contain sixteen non-inverting buffers with 3-STATE outputs. The device is nibble (4-bits) controlled with each nibble functioning identically, but independent of the other. The control pins can be shorted together to obtain full 16-bit operation.
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74LVT16244 * 74LVTH16244
Absolute Maximum Ratings(Note 3)
Symbol VCC VI VO IIK IOK IO ICC IGND TSTG Parameter Supply Voltage DC Input Voltage Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current DC Supply Current per Supply Pin DC Ground Current per Ground Pin Storage Temperature Value Conditions Units V V Output in 3-STATE Output in HIGH or LOW State (Note 4) VI GND VO GND VO ! VCC Output at HIGH State VO ! VCC Output at LOW State V mA mA mA mA mA
0.5 to 4.6 0.5 to 7.0 0.5 to 7.0 0.5 to 7.0 50 50
64 128
r64 r128 65 to 150
qC
Recommended Operating Conditions
Symbol VCC VI IOH IOL TA Supply Voltage Input Voltage HIGH Level Output Current LOW Level Output Current Free Air Operating Temperature Input Edge Rate, VIN 0.8V-2.0V, VCC 3.0V Parameter Min 2.7 0 Max 3.6 5.5 Units V V mA mA
32
64
40
0
85
10
qC
ns/V
't/'V
Note 3: Absolute Maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Note 4: IO Absolute Maximum Rating must be observed.
DC Electrical Characteristics
Symbol VIK VIH VIL VOH Parameter Input Clamp Diode Voltage Input HIGH Voltage Input LOW Voltage Output HIGH Voltage VCC (V) 2.7 2.7-3.6 2.7-3.6 2.7-3.6 2.7 3.0 VOL Output LOW Voltage 2.7 2.7 3.0 3.0 3.0 II(HOLD) (Note 5) II(OD) (Note 5) II Bushold Input Over-Drive Current to Change State Input Current Control Pins Data Pins IOFF IPU/PD IOZL IOZH IOZH Power Off Leakage Current Power Up/Down 3-STATE Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current 3-STATE Output Leakage Current Bushold Input Minimum Drive 3.0 3.0 3.6 3.6 3.6 0 0 - 1.5V 3.6 3.6 3.6 75 VCC 0.2 2.4 2.0 0.2 0.5 0.4 0.5 0.55 V V 2.0 0.8 TA
40qC to 85qC
Max
Min
Units V V V II
Conditions
1.2
18 mA
VO d 0.1V or VO t VCC 0.1V IOH IOH IOH IOL IOL IOL IOL IOL VI VI
100 PA 8 mA 32 mA
100 PA 24 mA 16 mA 32 mA 64 mA 0.8V 2.0V
75
500
PA PA
10
(Note 6) (Note 7) VI 5.5V 0V or VCC 0V V CC 0.5V to 3.0V GND or VCC 0.5V 3.0V VI VI VI
500 r1 5
1
PA
r100 r100 5
5 10
PA PA PA PA PA
0V d VI or VO d 5.5V VO VI VO VO
VCC VO d 5.5V
3
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74LVT16244 * 74LVTH16244
DC Electrical Characteristics
Symbol ICCH ICCL ICCZ ICCZ Parameter Power Supply Current Power Supply Current Power Supply Current Power Supply Current Increase in Power Supply Current (Note 8)
Note 5: Applies to bushold versions only (LVTH16244).
(Continued)
VCC (V) 3.6 3.6 3.6 3.6 3.6 TA
40qC to 85qC
Max 0.19 5.0 0.19 0.19 0.2
Units mA mA mA mA mA
Conditions Outputs High Outputs Low Outputs Disabled VCC d VO d 5.5V, Outputs Disabled One Input at VCC 0.6V Other Inputs at VCC or GND
Min
'ICC
Note 6: An external driver must source at least the specified current to switch from LOW-to-HIGH. Note 7: An external driver must sink at least the specified current to switch from HIGH-to-LOW. Note 8: This is the increase in supply current for each input that is at the specified voltage level rather than VCC or GND.
Dynamic Switching Characteristics
Symbol VOLP VOLV Parameter Quiet Output Maximum Dynamic VOL Quiet Output Minimum Dynamic VOL VCC (V) 3.3 3.3
(Note 9)
TA 25qC Typ 0.8 Max Units V V CL Conditions 50 pF, RL (Note 10) (Note 10) 500:
Min
0.8
Note 9: Characterized in SSOP package. Guaranteed parameter, but not tested. Note 10: Max number of outputs defined as (n). n1 data inputs are driven 0V to 3V. Output under test held LOW.
AC Electrical Characteristics
TA Symbol Parameter CL VCC Min tPLH tPHL tPZH tPZL tPHZ tPLZ tOSHL tOSLH Output to Output Skew (Note 11) Output Disable Time Output Enable Time Propagation Delay Data to Output 1.2 1.2 1.2 1.2 2.0 1.5 3.3V r 0.3V Max 3.5 3.5 4.0 5.0 4.7 4.2 1.0 Min 1.2 1.2 1.2 1.2 2.0 1.5
40qC to 85qC
50 pF, RL 500: VCC 2.7V Max 3.9 3.9 5.0 6.5 5.2 4.4 1.0 ns ns ns ns Units
Note 11: Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH-to-LOW (tOSHL) or LOW-to-HIGH (tOSLH).
Capacitance
Symbol CIN COUT
(Note 12)
Parameter Conditions VCC VCC 0V, VI 0V or VCC 0V or VCC 3.0V, VO Typical 4 8 Units pF pF
Input Capacitance Output Capacitance
Note 12: Capacitance is measured at frequency f
1 MHz, per MIL-STD-883, Method 3012.
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74LVT16244 * 74LVTH16244
Physical Dimensions inches (millimeters) unless otherwise noted
54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide Package Number BGA54A
5
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74LVT16244 * 74LVTH16244
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Small Shrink Outline Package (SSOP), JEDEC MO-118, 0.300" Wide Package Number MS48A
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74LVT16244 * 74LVTH16244 Low Voltage16-Bit Buffer/Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Package Number MTD48
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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